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rx if/bba with gps s1m8662a ( preliminary) 1 introduction s1m8662a is cdma/pcs/gps triple mode if/ baseband ic which is divided into three main parts - if frequency processing, basband processing , and digital interface. the receiver ic (s1m8662a)and transmitter ic (s1m8657) are provided as a kit. s1m8662a is a receiver ic, installed with a rx agc, baseband converter, baseband analog filter, and a-d converter. it can send a digital baseband signal to the digital baseband ic. s1m8662a is fabricated on the samsung's 0.5um high-speed, high frequency bicmos processing and can achieve superior high frequency and low power digital operations. its operating voltage is 2.7 to 3.3v, and operating temperature -30 to +85 c . features cellular cdma/pcs/gps triple mode agc input signal range : 90db qpsk baseband converter built-in i ,q baseband signal extractor lpf built-in 4-bit adc for converting i and q cdma analog baseband signals to digital baseband signals built-in vco for baseband conversion built-in modem pdm control circuit to compensate the i and q offsets built-in tcxo output on/off 3-line serial port interface (spi) operating voltage : 2.7 to 3.3v 32bcc++(5mm * 5mm * 0.8mm) package ordering information device package operating temperature ++ s1m8662ax01-f0t0 32-bcc++-5.0 5.0 -30 to +85 c ++ : under development 32-bcc++-5.0 5.0
s1m8662a ( preliminary) rx if/bba with gps 2 block diagram sw crx_if1 crx_if2 ragc_cont grx_if1 grx_if2 rxvco_out1,2 q_ofs chipx8 rxqd[0] - [3] rxid[0] - [3] i_ofs rxvco_t1 rxvco_t2 tcxo_in clock data strobe n=2,3,4,6 tcxo_out vco 0 div. n 90 cdma lpf gps lpf cdma lpf gps lpf offset control spi control 4-bit adc x1 4-bit adc
rx if/bba with gps s1m8662a ( preliminary) 3 pin configuration crx_if2 tcxo_out spi_data spi_stb rxvco_out1 rxid[0] vddd vdda rxid[1] ragc_cont grx_if1 grx_if2 crx_if1 vdda vdda vdda q_ofs i_ofs rxvco_t1 rxvco_t2 rxvco_out2 spi_clk tcxo_in chipx8 rxqd[3] rxqd[2] rxqd[1] rxqd[0] vddm rxid[3] rxid[2] vdda s1m8662a (top view) gnd slug 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 16 15 14 13 12 11 10 24 23 22 21 20 19 17 18
s1m8662a ( preliminary) rx if/bba with gps 4 pin description pin no symbol i/o description 1 vddd p power for the digital logic. 2 vdda p power input terminal for the analog circuit. 3 ragc_cont ai agc gain control input. the input voltage is allowed up to vdda. it remains at high impedance during sleep. 4 5 grx_if1 grx_if2 ai gps if input terminals, which have an input impedance of about 865w; generally, the gps if saw filter is connected to them. when these terminals are not used, they remain at high impedance. 6 7 crx_if1 crx_if2 ai cdma if input terminals, which have an input impedance of about 865 w ; generally, the cdma if saw filter is connected to them. when these terminals are not used, they remain at high impedance. 8 vdda p power input terminal for the analog circuit. 9 tcxo_out do tcxo clock output. division ratio : 1 10 vdda p power input terminal for the analog circuit. 11 vdda p power input terminal for the analog circuit. 12 13 q_ofs i_ofs ai control dc input for removing the dc offset generated in the s1m8662a and system during cdma and gps mode. the control dc is generated in the modem in pdm form, passes through the r-c filter and is converted to dc, which is sent to this input terminal. 14 15 rxvco_t1 rxvco_t2 ai very sensitive terminal, which is connected to the oscillation l-c resonance circuit. their impedance are about 2k w 16 vdda p power input terminal for the analog circuit. 17 18 rxvco_out1 rxvco_out2 ao output for the pll, able to output about -12dbm. when this is not used, it remains at high impedance. 19 spi_stb di 3-line serial control. strobe input port. if this pin is opened, it remains at low. 20 spi_data bi 3-line serial control. data input/output port. if this pin is opened, it remains at low. 21 spi_clk di 3-line serial control. clock input/output port. if this pin is opened, it remains at low. 22 tcxo_in ai/di reference frequency input terminal connected to the vctcxo output. when this pin stops, only dc bias is delivered to maintain the dc charge value of the capacitor connected externally 23 chipx8 di chipx8 clock input port. cdma/gps adc sampling clock from the msm.
rx if/bba with gps s1m8662a ( preliminary) 5 pin description ( continued) pin no symbol i/o description 24 25 26 27 rxqd3 rxqd2 rxqd1 rxqd0 do q channel 4-bit a-d converter's digital outputs, which are connected to the modem data input pins. these data are synchronized at chip 8's rising edge and output. because they are valid at the falling edge, the data are latched at the falling edge in the modem. 28 vddm di power source for a logic circuit ,related to the digital input /output, connected to an external digital logic such as the modem. 29 30 31 32 rxqd3 rxqd2 rxqd1 rxqd0 do i channel 4-bit a-d converter's digital outputs, which are connected to the modem data input pins. these data are synchronized at chip 8's rising edge and output. because they are valid at the falling edge, the data are latched at the falling edge in the modem. table 1. s1m8660a and s1m8662a function & control content comparison function / mode control s1m8660a s1m8662a operation modes cdma (cellular cdma, pcs) amps (fm) global positioning system (gps) if agc 90db range cdma (cellular cdma, pcs) amps (fm) global positioning system (gps) if to analog baseband quadrature down-conversion cdma (cellular cdma, pcs) amps (fm) global positioning system (gps) low pass baseband i/q filtering with mode specific performance cdma (cellular cdma, pcs) amps (fm) global positioning system (gps) 4-bit i/q analog to digital converters, parallel outputs cdma (cellular cdma, pcs) global positioning system (gps) 8-bit i/q analog to digital converters, serial outputs amps (fm) rx slotting operation for saving current consumption clock generation tcxo/n output d (n=1) configurable chipx8 as input or output d (input) vco for generation the rx if lo analog baseband amplifiers with i/q offset controls
s1m8662a ( preliminary) rx if/bba with gps 6 absolute maximum ratings characteristic symbol value power supply v cc -0.5 to 3.6v storage temperature t stg -55 to +125 c operating temperature t opr -30 to +85 c storage temperature hbm tbd electrostatic discharge rating mm tbd recommended operating conditions characteristic symbol value power supply v dda , v ddd 2.7 to 3.3v v ddm 2.4 to 3.3v ambient operating temperature ta -30 to +85 c electrical characteristics electrical characteristics(v cc = 3.3v, ta = 25 c) characteristic test conditions symbol min typ max units current consumption cdma idle mode i crx - 23 30 ma current consumption cdma sleep mode i cslp - 300 650 ua current consumption cdma slot mode i cslt - 5 7 ma current consumption gps idle mode i gps - 24 31 ma logic high input v ih v ddm -0.4 - - v logic low input v il - - 0.4 v logic high output v oh v ddm -0.4 - - v logic low output v ol - - 0.4 v digital input capacitance c di - - 5 pf digital output load capacitance c dol - - 10 pf tcxo input impedance attach c = 2pf z tcxo 10 - - k w vco input resistance if vco differential r vco - 2.0 - k w vco input capacitance if vco differential c vco - - 2 pf
rx if/bba with gps s1m8662a ( preliminary) 7 ac characteristics characteristic test conditions symbol min typ max unit cdma performance input sensitivity maximum agc gain. control input signal so that output corresponding to 3lsb is output from adc. vcsen -102 - - dbm maximum input signal minimum agc gain. control input signal so that output corresponding to 3lsb is output from adc. vcmax - - -12 dbm agc gain slope pdm 3.3v mode gs lope 43 50 57 db/v agc gain error over temperature -30 to +85 c. gvar -3 - 3 db if input frequency range cin < 2pf fin - - 250 mhz if input impedance zin 0.8 1.0 1.2 k w input power = -102dbm nfmin - - 7 db noise figure input power = -75dbm nfmid - - 20 db input power = -25dbm nfmax - - 72 db iip3 agc gain max. iip3max -53 - - dbm agc gain min. iip3min -10 - - dbm spurious contents adc generated harmonic frequency component. two signals in the in-band are each mixed with signals which will allow adc to produce -7db output signals. the harmonic and non-harmonic components of the adc output signals between 1khz to 20mhz are extracted and added. the agc control voltage is controlled so that adc output is full scale when the input signal is -80dbm. tspur - - -25 dbc spurious content related to jammer in-band spurious peak value produced by imd based on 2 jammer signals. one in-band signal(@50khz,0.5*f/s) and two jammers(@900khz, 22db*f/s and @1.7mhz, 21db*f/s)are simultaneously input. agc control voltage is controlled so that adc output is f/s when the input signal is -80dbm. jspur - - -18.4 dbc
s1m8662a ( preliminary) rx if/bba with gps 8 ac characteristics (continued) characteristic test conditions symbol min typ max unit single-tone jammer desense overall gain reduction due to one jammer. the in-band signal at -97dbm (control the agc control voltage to 0.5*f/s)and the jammer signal at 900khz and -57dbm are simultaneously input. jdsen - - 1.0 db residual sideband rsb k k k k = + + + - 20 1 2 1 2 2 2 log cos cos q q k : linear gain mismatch q : phase mismatch in deg. rsb 22 db offset gain slope amount of code change of the voltage adc output at the i/q offset control gofs - 250 - %fs/v offset adjust input impedance - zoff 100 - - k w out-band 3 900khz atc9 46 - - db attenuation 3 1.2mhz atc12 48 - - db gain flatness amount of gain change along i and q paths between 1khz to 615khz gft -1 1 db if vco pertormance vco and buffered output frequency range vco external time constant and pll value fvco - 170 500 mhz vco phase noise tank lc's q value should be above 20. measure @100khz away from the mid- frequency. pvco - - 104 dbc/hz rxvco_out output power select a vco buffer output value reduced by -2db. connect output load to 50 w . ovco -15 - - dbm
rx if/bba with gps s1m8662a ( preliminary) 9 ac characteristics (continued) characteristic test conditions symbol min typ max unit gps performance input sensitivity maximum agc gain. control input signal so that adc outputs 0.5*f/s. vcsen -102 - - dbm maximum input signal minimum agc gain control input signal so that adc outputs 0.5*f/s. vcmax - - -12 dbm agc gain slope pdm 3.3v mode gslope 43 50 57 db/v agc gain error over temperature -30 c to +85 c. gvar -3 - 3 db if input frequency range cin < 2pf fin - - 250 mhz if input impedance zin 0.8 1.0 1.2 k w input power = -98dbm nfmin - - 7 db noise figure input power = -75dbm nfmid - - 12 db input power = -25dbm nfmax - - 58 db iip3 agc gain max. iip3max -53 - - dbm agc gain min. iip3min -25 - - dbm offset gain slope amount of code change of the voltage adc output at the i/q offset control gofs 250 %fs/ v offset adjust input impedance - zoff 100 - - k w out-band 3 1.3mhz atc13 46 - - db attenuation 3 1.7mhz atc17 48 - - db residual sideband rsb k k k k = + + + - 20 1 2 1 2 2 2 log cos cos q q k : linear gain mismatch q : phase mismatch in deg. rsb 22 - - db gain flatness amount of gain change along i and q paths between 1khz to 800khz gft -1.5 - 1.5 db
s1m8662a ( preliminary) rx if/bba with gps 10 timing diagrams 90% 10% 3 - 12ns 3 - 12ns 101.7ns (9.8304mhz) 50.9 + 10ns 50.9 + 10ns 20ns over 15ns over valid data valid data valid data figure 1. cdma receive adc timing 90% 10% 3 - 12ns 3 - 12ns 122.2ns (8.184mhz) 61.1ns 61.1ns 20ns over 15ns over valid data valid data valid data figure 2. gps receive adc timing 50ns over valid data 50ns over 0.6 - 10us 50ns over 50ns over spi_data hold time spi_data hold time spi_strobe setup time spi_strobe hold time clock duty : 35 - 65% rising time 25ns under falling time 25ns under spi_stb spi_clk spi_data figure 3. 3-line serial port interface timing
rx if/bba with gps s1m8662a ( preliminary) 11 functional description s1m8662a is a cdma/gps receive-only baseband analog ic, located between the rf mid-frequency processing terminal and baseband processing terminal. the rf analog mid-frequency signal terminal(if saw filter output), directly connected to the s1m8662a mid-frequency input pin, converts and processes the baseband signal and sends the corresponding digital signal to the modem ic. baseband analog processing uses qpsk modulation, lpf, and a-d converter and the modem ic performs digital cdma /gps baseband modulation on the digitalized analog baseband signal it receives. an on-chip vco creates a multiple frequency(x2, x3, x4, x6) lo signal. s1m8662a uses a 0.5um bicmos, equipped with high-frequency bipolar and low power standardized cmos logic, to operate safely in the low power range, consisting of power voltage between 2.7 to 3.3v and operating temperature between -30 to +85 c. cdma receive signal path the receive circuit of s1m8662a has the rx agc, an automatic gain controller, and baseband lpf and output terminal with the a-d converter, and vco and mixer etc. the input signal is received as a differential signal, which is modulated to 1.23 mhz spread-spectrum for cdma. the mid-frequency is 220.38mhz for korea-pcs, 1.23mhz for us-pcs, and 85.38mhz for cellular; they are set based on the time constants of the components involved with the external vco and external rx pll. rx agc , connected to both the if saw filter and matching component in the rf-if converter output located in the rf block, amplifies or reduces according to the signal size. it takes its orders from the modem chip when it sets the appropriate receive level as required by the cdma system. gain is controlled by applying a dc voltage to the ragc_cont pin. the applied dc is produced when the pdm signal, generated as a control signal in the modem, passes through the r-c filter. the control band of this agc is approx. 90db. the qpsk baseband modulator separates and modulates the if signal sent by the agc using i(in-phase) and q(quad-phase) baseband signal. essentially, two signals, i-lo and q-lo (local oscillator), are mixed with agc's if output signals, respectively. the lo(local oscillator) signal is generated by the internal oscillating components, externally connected tank coil, and varactor, and the externally independent pll device is used to generate its exact oscillation mid-frequency. t=0 q-ch i-ch figure 4. received i/q phase in s1m8662a defining of the i-phase and q-phase receive path is very important to its design. the polarities of these paths are also important to digital baseband modulation. therefore, the output of the qpsk baseband modulation determines the i and q phases; i-phase is defined as the phase leading the q-phase by exactly 90 , but it simpler to think of i as cosin and q as sin. the figure related to this is shown in figure 5. this definition is valid only when the qpsk if input signal is higher than the if mid-frequency. the baseband signal, output by the qpsk modulator, includes various other unnecessary surrounding band noises, which are removed by the use of the lpf(low-pass-filter). ultimately, i and q filtered signals are converted to digital signals by the 4-bit a-d converter and sent to the modem. the a-d converter used is a parallel output type and its outputs are synchronized at the chip 8 rising edge. the modem chip captures the data on the chip 8 falling edge. the chip 8 clock used in the a-d converter received to msm.
s1m8662a ( preliminary) rx if/bba with gps 12 gps rx signal path the difference of the s1m8662a from the s1m8656a is that s1m8662a provides gps receiving operation. while gps receiving path shares function blocks with cdma modes, it needs independent agc and lowpass filter. gps if signal from gps rf-if mixer is applied to s1m8662a via gps saw filter. gps if is differential input pins. the operation of i/q demodulator is the same in cdma modes and the phase relation of i/q signal of the output is the same as depicted in figure 5. gps lowpass filter of s1m8662a has its cut off frequency at around 800khz. a-d converter, as output of gps path, is the 4bit parallel converter which is the same one used in cdma path. but the sampling frequency is different from that of cdma mode. and in operating in gps mode, sampling clock of a-d converter should be supplied from the modem. tcxo clock generator in s1m8656a and s1m8660a, the output of tcxo is divided by 1, 2, and 4 and then clocked out. but in s1m8662a the output of tcxo is just amplified and clocked out. so, there is no spi control which controls the division ratio of tcxo clock. in this product, the tcxo_in pin can input both tcxo signal ( tcxo_sig) and tcxo control ( tcxo_cont) at the same time. buffer tcxo_sig tcxo_out tcxo_cont c r s1m8662a 22 lpf x1 9 figure 5. tcxo clock generating if tcxo_cont pin is held low or high-impedance (floating), tcxo_out keeps high, and on the contrary, if tcxo_cont pin is held high, tcxo_out outputs tcxo clock. if tcxo_cont pin is low or high-impedance (floating), s1m8662a can be pin to pin compatible with ifr3500 of qualcomm.
rx if/bba with gps s1m8662a ( preliminary) 13 rx voltage controlled oscillator(vco) s1m8662a includes the rx lo block having the vco and quad-phase generator. the quad-phase generator outputs i-phase and q-phase clocks with 1/2, 1/3, 1/4 or 1/6 the vco frequency and sends them to the qpsk modulator. the vco buffer is used when the vco output is sent to the external rx pll. although the allowable vco frequency is determined based on an external time constant, it can only range between approx. 100mhz to 500mhz, suggesting that the maximum input if frequency is 250mhz. serial port interface(spi) s1m8662a is equipped with the serial i/f. all internal functions can be controlled through a common bus using an external controller. s1m8662a is designed to be completely compatible with msm series of qualcomm. here, the modem is the master and s1m8662a the slave. each pin which uses the spi bus has the following common functions. the stb(strobe) for the serial bus start signal is used to initialize serial data transmission. serial bus data is used for the bi-direction data input /output at serial data transmission. because it is an open drain type pin, it requires the pull-up resistance of approx. 8k w . serial bus clk is used to synchronize the data input/output at serial data transmission. serial port interface operation the modem, the master, controls slaves such as s1m8662a using the spi bus. the stb falling edge indicates the start of the serial i/f data transmission. the stb becomes high to mark the end of the data transmission. (data sent after the stb turns high are not valid.) serial line data is captured and stored as soon as the bba or the modem places the clock on the falling edge. the spi 3-line must remain high for at least 1-clock cycle in order to sent new data. the msb always outputs the data line data. after 9-clocks, which is required to send data, the data line driver opens the data line, at which time the data line becomes high because of the external pull-up resistance. serial data transfer format s1m8662a and s1m8657 are all slave devices with the spi bus. what differentiate them from one another is their different device ids. each company has its own characteristic spi bus configuration , but normally the 3-line bus is most often used and sometimes the 2-line bus such as the iic bus. figure 7. shows the serial data transfer format.
s1m8662a ( preliminary) rx if/bba with gps 14 mode=01 dummy 1=master read master drive slave address start bit stb clk data d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 master drive register address slave drive data master drive register address master drive data end bit dummy dummy 0=master read dummy dummy figure 6. serial data transfer format (1) the first 2-bits are for transmission only and this product must send '01'.(others are not permitted.) (2) the following 6-bit data specifies the slave device, which is connected to the spi bus and has its own id. (3) the following 1-bit is a dummy bit, which marks the end of the 8-bit data transmission and the beginning of the next data to be sent. (4) the following 1-bit decides on whether the master will drive the data line or the slave will. if this bit is '1', the master will drive , but if '0' the slave will drive the data line. (5) the following 7-bit data is the register address of the specified slave device; the 7-bits for an address allows 128 register addresses for slaves. (6) the following high 1-bit data is a dummy data. (7) the following 8-bit data is the data in the device to be driven. (8) the following 1-bit data is a dummy data, which marks the end of the 8-bit data transmissi on and beginning of the next data to be sent. (9) the following 1-bit decides on whether the master will drive the data line or the slave will. if this bit is '1', the master will drive , but if '0' the slave will drive the data line. (10) the following 7-bit data is the register address of the specified slave device. (11) the following high 1-bit data is a dummy data. (12) the following 8-bit data is the data in the device to be driven. ( continous data transmission such as this can be ended with a 1-byte transmission or can be read/written repeatedly.) (13) after the last data is sent, the data line opens and becomes high; (14) the clk continues for half the 1-clock cycle and then becomes high; (15) and the stb becomes high as soon as the clock becomes high and this marks the end of data transmission.
rx if/bba with gps s1m8662a ( preliminary) 15 modes of operation s1m8662a can be controlled by the spi bus. table 2 shows the various modes. table 2. mode control in the dc control mode mode 0x03[1:0] block_ctl 0x06[7] vco_ctl 0x052:0] filter_sel chipx8 sleep 00 x xxx all circuit are off cdma idle(rx) 01 or 11 0 100 cdma mode gps idle(rx) 01 or 11 1 111 cdma mode cdma sot 10 0 100 all circuit are off except the vco, vco buffer gps slot 10 1 111 not used
s1m8662a ( preliminary) rx if/bba with gps 16 control registers s1m8662a has various registers which can be programmed by the spi bus. these registers have their own function which are described below. table 3. s1m8660a control registers register name address r/w default vale description reset 0x00 w - reset. reset s1m8662a and all the register values are returned to their default value. spi_id 0x01 r 0x1f spi_id. each slave device has its own, independent code; s1m8662a code is 1e. block_ctl 0x03 r/w 0x8 block_ctl decides on the s1m8662a operation mode. lo division ratio. controls vco output. filter_sel. 0x05 r/w 0x1c. filter_sel. lowpass filter selection vco_ctl 0x06 r/w 0x0b vco_ctl. controls the vco operation and vco output. w : modem is recorded in the s1m8662a register r : when s1m8662a sends data to the modem table 4. description of control registers address name type bits description 00(h) reset w - when the master uses this register, the s1m8662a returns all the programmed register values to their initial value. 01(h) spi_id r [5:0] this read-only register is used to confirm the type of slave connected to the master. it is set to 1eh and all s1m8662a has the same value. this is the id absolutely required to differentiate the controller from the data, when there are many slaves connected to the spi bus.
rx if/bba with gps s1m8662a ( preliminary) 17 table 4. description of control registers (continued) address name type bits description [7] identifies the s1m8662a default = 1 [6] default = 0, reserved registers 03(h) block_ctl r/w [5:4] if lo divider, default = 00 00 : 2, 01 : 3 10 : 4, 11 : 6 [3] default = 1, reserved registers [2] rxvco_out2. default = 1 1 : singled ended output (rxvco_out1 active, rxvco_out2 off) 0 : differential output (rxvco_out1, 2 active) [1:0] mode. default = 00 00 : sleep, 01 : receive 10 : rx slot, 11 : receive 05(h) filt_sel r/w [7:2] default = 0001 11 reserved registers [1:0] filt_sel default = 00 00 : cdma lpf 10 : gps lpf 06(h) vco r/w [7] gps_sel default = 0 0 : gps mode disabled 1 : gps mode abled [6:3] default = 0001 reserved registers [2] cco_ctl default = 0 0 : rx_vco low drive 1 : rx_vco low max [1] default = 11. reserved registers
s1m8662a ( preliminary) rx if/bba with gps 18 characteristic graph +1.5 1k frequency [hz] relative amplitude [db] +0.5 -1.5 -4.0 -46.0 -48.0 750k 800k 1.1m 1.3m 1.7m figure 7. gps rx low pass filter mask gain mismatch [db] 10 8 3 2 1 0 7 6 5 4 9 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 phase mismatch [deg] region of acceptable mismatch performance figure 8. gps rx gain/phase mismatch specification
rx if/bba with gps s1m8662a ( preliminary) 19 characteristic graph (continued) 10 100 1k 10k 100k 1m -120 phase noise(dbc/hz) -110 -100 -90 -80 -70 -60 -50 -40 -30 frequency offset(hz) figure 9. s1m8662a if vco open loop phase noise
s1m8662a ( preliminary) rx if/bba with gps 20 characteristic graph (continued) 100 80 30 20 10 0 70 60 50 40 90 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 if input power [dbm] noise figure [db] region of acceptable nf performace figure 10. gps rx mode noise figure specification 0 -10 -20 -30 -40 -50 -60 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 iip3 [dbm] if input power [dbm] region of acceptable iip3 performance figure 11. gps rx mode iip3 specification
rx if/bba with gps s1m8662a ( preliminary) 21 test circuit 1:8 10nf 10nf 1:8 2pf 2pf 1k 10nf 10nf 2.3nh vif gps cdma sw 4.7k vcont vddd vdda vdda tcxo_out vdda vdda vqoffset vioffset 1pf 1sv279 100nh 47pf 1nf 10k vtune vdda 1nf rxvco_out2 1nf rxvco_out1 spi_stb spi_clk spi_data tcxo_in chipx8 q_outpu t i_output vddm 1nf tcxo_cont vdda vddd vddm 10uf 10nf 10nf 10nf 10nf 10nf 10nf 10nf 10k vddm s1m8662a gnd slug 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 16 15 14 13 12 11 10 24 23 22 21 20 19 17 18 4-bit dac 4-bit dac 1k 2.3nh 2pf 2pf spi_stb : serial interface strobe spi_clk : serial interface clock spi_data : serial interface data 47pf 10k 10k 10k 10uf 10uf figure 12. test circuit
s1m8662a ( preliminary) rx if/bba with gps 22 package dimension 32bcc+ package outline #1 #25 #17 #1 #9 #1 index laser mark 5.00 + 0.10 5.00 + 0.10 5.00 + 0.10 0.075 + 0.025 0.80 max 0.30 + 0.1 0.50 + 0.1 0.40 + 0.1 0.45 + 0.1 0.45 + 0.1 3.10 + 0.1 3.50 + 0.1 5.0 + 0.1

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